1. Technical Field
The present invention relates to a semiconductor integrated circuit and, more particularly, to a high input voltage tolerant input/output circuit being free from electrostatic discharge (ESD) voltage.
2. Description of the Related Art
Semiconductor devices comprising circuits that operate on a low-voltage power supply and circuits that operate on a high-voltage power supply are known. There are semiconductor device manufacturers producing 3V products (3V referring to any low operating voltage device). There are manufacturers producing components that take 5V power. It can be desirable to interface, for example, 3V and 5V devices in a mixed voltage system that is high input voltage tolerant.
FIG. 1 is a circuit diagram illustrating a conventional high input voltage tolerant input/output circuit 1. Referring to FIG. 1, first and second PMOS transistors 12 and 14 are parallel connected between a power supply voltage VDD and a pad 10. First and second NMOS transistors 16 and 18 are serially connected between the pad 10 and a ground voltage VSS. The second NMOS transistor 18 is parallel connected to a third NMOS transistor 19. A first internal signal PG is received by the gates of the first and second PMOS transistors 12 and 14, and a second internal signal NG is received by the gates of the second and third NMOS transistors 18 and 19. The gate of the first NMOS transistor 16 is connected to the power supply voltage VDD. An output signal having a predetermined output voltage is output to the pad 10 in response to the first and second internal signals PG and NG. An input signal received by the pad 10 is transmitted to an internal circuit.
In the conventional high input voltage tolerant input/output circuit 1, when a high voltage such as 5V is applied to the pad 10 at power supply voltage VDD of 3.3V, the gate of the first NMOS transistor 16 is connected to the 3.3V power supply voltage VDD and a voltage of 1.7V is applied to a gate oxide film of the first NMOS transistor 16. Hence, the first NMOS transistor 16 is stable when 5V is applied to the pad 10.
However, when an electrostatic discharge (ESD) voltage of several hundreds or thousands of Volts is applied to the pad 10 during a test for ESD voltage, the first NMOS transistor 16 is destroyed. As shown by the path labeled “A” in FIG. 1, positive ESD voltage applied to the pad 10 is discharged to the power supply voltage VDD via a P-N diode formed as a junction between the first and second PMOS transistors 12 and 14. When this occurs, the EDS voltage is applied to the gate of the first NMOS transistor 16 because the power supply voltage VDD is connected to the gate, and the gate oxide film is destroyed. On the other hand, as shown by the path labeled “B”, a negative ESD voltage is discharged to the ground voltage VSS via an N-P diode formed as a junction between the first and second NMOS transistors 16 and 18.
There remains a need for a high input voltage tolerant input/output circuit being free from ESD voltage.